SH7263 Datasheet, PDF (1435/1862 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7260 Series

Section 26 LCD Controller (LCDC)
26.4 Operation
26.4.1 LCD Module Sizes which can be Displayed in this LCDC
This LCDC is capable of controlling displays with up to 1024 × 1024 dots and 16 bpp (bits per
pixel). The image data for display is stored in VRAM, which is shared with the CPU. This LCDC
should read the data from VRAM before display.
This LSI has a maximum 32-burst memory read operation and a 2.4-kbyte line buffer, so although
a complete breakdown of the display is unlikely, there may be some problems with the display
depending on the combination. A recommended size at the frame rate of 60 Hz is 320 × 240 dots
in 16 bpp or 640 × 480 dots in 8 bpp.
As a rough standard, the bus occupation ratio shown below should not exceed 40%.
Overhead coefficient x Total number of display pixels ((HDCN + 1) x 8 x (VDLN + 1))
x Frame rate (Hz) x Number of colors (bpp)
Bus occupation ratio (%) =
CKIO (Hz) x Bus width (bit)
x 100
The overhead coefficient becomes 1.375 when the CL2 SDRAM is connected to a 32-bit data bus
and 1.188 when connected to a 16-bit data bus.
Rev. 2.00 Mar. 14, 2008 Page 1401 of 1824
REJ09B0290-0200