SH7263 Datasheet, PDF (358/1862 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7260 Series

Section 9 Bus State Controller (BSC)
(3) Burst Read
A burst read occurs in the following cases with this LSI.
• Access size in reading is larger than data bus width.
• 16-byte transfer in cache miss.
• 16-byte transfer by DMAC
• 16-byte to 128-byte transfer by LCDC
This LSI always accesses the SDRAM with burst length 1. For example, read access of burst
length 1 is performed consecutively 4 times to read 16-byte continuous data from the SDRAM that
is connected to a 32-bit data bus. This access is called the burst read with the burst number 4.
Table 9.17 shows the relationship between the access size and the number of bursts.
Note: For details, see section 26, LCD Controller (LCDC).
Table 9.17 Relationship between Access Size and Number of Bursts
Bus Width
Access Size
Number of Bursts
16 bits
8 bits
1
16 bits
1
32 bits
2
16 bits
8
32 bytes*
16
64 bytes*
32
128 bytes*
64
32 bits
8 bits
1
16 bits
1
32 bits
1
16 bits
4
32 bytes*
8
64 bytes*
16
128 bytes*
32
Note: * 32-, 64-, or 128-byte access occurs when the LCDC is used. For details, see section
26, LCD Controller (LCDC).
Rev. 2.00 Mar. 14, 2008 Page 324 of 1824
REJ09B0290-0200