SH7263 Datasheet, PDF (1052/1862 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7260 Series

Section 20 IEBus^TM Controller (IEB)
(3) Slave Address Field
The slave address field is a field to transmit an address (the slave address) of a unit (the slave unit)
to be transmitted. The slave address field is comprised of slave address bits, a parity bit, and an
acknowledge bit.
The slave address consists of 12 bits and the MSB is output first. The parity bit is output after the
12-bit slave address is transmitted to avoid receiving the slave address accidentally. The master
unit then detects the acknowledgement from the slave unit to confirm that the slave unit exists on
the bus. When the acknowledgement is detected, the master unit enters the control field output
state. However, the master unit enters the control field output state without detecting the
acknowledgement in broadcast communications.
The slave unit returns an acknowledgement when the slave addresses match and the parities of the
master and slave addresses are correct. When the parity of either the master or slave address is
incorrect, the slave unit decides that the master or slave address was not correctly received and
does not return the acknowledgement. In this case, the master unit enters the waiting (monitor)
state and communications ends.
In the case of broadcast communications, the slave address is used to identify the type of broadcast
communications (group or general) as follows:
• When the slave address is H'FFF: General broadcast communications
• When the slave address is other than H'FFF: Group broadcast communications
Note: The group number is the upper 4-bit value of the slave address in group broadcast
communications.
(4) Control Field
The control field is a field for transmitting the type and direction of the following data field. The
control field is comprised of control bits, a parity bit, and an acknowledge bit.
The control bits consist of four bits and the MSB is output first.
The parity bit is output following the control bits. When the parity is correct, and the slave unit
can implement the function required from the master unit, the slave unit returns an
acknowledgement and enters the message length field output state. However, if the slave unit
cannot implement the requirements from the master unit even though the parity is correct, or if the
parity is not correct, the slave unit does not return an acknowledgement and returns to the waiting
(monitor) state.
Rev. 2.00 Mar. 14, 2008 Page 1018 of 1824
REJ09B0290-0200