SH7263 Datasheet, PDF (856/1862 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7260 Series

Section 16 Synchronous Serial Communication Unit (SSU)
16.5 SSU Interrupt Sources and DMAC
The SSU interrupt requests are an overrun error, a conflict error, a receive data register full,
transmit data register empty, and a transmit end interrupts. Of these interrupt sources, a receive
data register full, and a transmit data register empty can activate the DMAC for data transfer.
Since both an overrun error and a conflict error interrupts are allocated to the SSERI vector
address, and both a transmit data register empty and a transmit end interrupts are allocated to the
SSTXI vector address, the interrupt source should be decided by their flags. Table 16.8 lists the
interrupt sources.
When an interrupt condition shown in table 16.8 is satisfied, an interrupt is requested. Clear the
interrupt source by CPU or DMAC data transfer.
Table 16.8 SSU Interrupt Sources
Abbreviation Interrupt Source
SSERI
Overrun error
Conflict error
SSRXI
Receive data register full
SSTXI
Transmit data register empty
Transmit end
Interrupt Condition
(RIE = 1) • (ORER = 1) +
(CEIE = 1) • (CE = 1)
(RIE = 1) • (RDRF = 1)
(TIE = 1) • (TDRE = 1) +
(TEIE = 1) • (TEND = 1)
DMAC Activation
⎯
Possible
Possible
Rev. 2.00 Mar. 14, 2008 Page 822 of 1824
REJ09B0290-0200