SH7263 Datasheet, PDF (549/1862 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7260 Series

Section 11 Multi-Function Timer Pulse Unit 2 (MTU2)
11.4 Operation
11.4.1 Basic Functions
Each channel has a TCNT and TGR register. TCNT performs up-counting, and is also capable of
free-running operation, cycle counting, and external event counting.
Each TGR can be used as an input capture register or output compare register.
Always select MTU2 external pins set function using the pin function controller (PFC).
(1) Counter Operation
When one of bits CST0 to CST4 in TSTR is set to 1, the TCNT counter for the corresponding
channel begins counting. TCNT can operate as a free-running counter, periodic counter, for
example.
(a) Example of Count Operation Setting Procedure
Figure 11.4 shows an example of the count operation setting procedure.
Operation selection
Select counter clock [1]
Periodic counter
Select counter clearing
source
[2]
Select output compare _[3]
register
Set period
[4]
Start count operation [5]
<Periodic counter>
Free-running counter
Start count operation [5]
<Free-running counter>
[1] Select the counter clock
with bits TPSC2 to TPSC0
in TCR. At the same time,
select the input clock edge
with bits CKEG1 and
CKEG0 in TCR.
[2] For periodic counter
operation, select the TGR
to be used as the TCNT
clearing source with bits
CCLR2 to CCLR0 in TCR.
[3] Designate the TGR
selected in [2] as an output
compare register by means
of TIOR.
[4] Set the periodic counter
cycle in the TGR selected
in [2].
[5] Set the CST bit in TSTR to
1 to start the counter
operation.
Figure 11.4 Example of Counter Operation Setting Procedure
Rev. 2.00 Mar. 14, 2008 Page 515 of 1824
REJ09B0290-0200