SH7263 Datasheet, PDF (646/1862 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7260 Series

Section 11 Multi-Function Timer Pulse Unit 2 (MTU2)
11.7.9 Contention between TGR Read and Input Capture
If an input capture signal is generated in the T1 state of a TGR read cycle, the data that is read will
be the data in the buffer before input capture transfer.
Figure 11.104 shows the timing in this case.
TGR read cycle
T1 T2
Pφ
Address
TGR address
Read signal
Input capture
signal
TGR
N
M
Internal data
bus
N
Figure 11.104 Contention between TGR Read and Input Capture
Rev. 2.00 Mar. 14, 2008 Page 612 of 1824
REJ09B0290-0200