SH7263 Datasheet, PDF (346/1862 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7260 Series

Section 9 Bus State Controller (BSC)
(2) Address Multiplexing
An address multiplexing is specified so that SDRAM can be connected without external
multiplexing circuitry according to the setting of bits BSZ[1:0] in CSnBCR, bits A2ROW[1:0],
and A2COL[1:0], A3ROW[1:0], and A3COL[1:0] in SDCR. Tables 9.11 to 9.16 show the
relationship between the settings of bits BSZ[1:0], A2ROW[1:0], A2COL[1:0], A3ROW[1:0], and
A3COL[1:0] and the bits output at the address pins. Do not specify those bits in the manner other
than this table, otherwise the operation of this LSI is not guaranteed. A25 to A18 are not
multiplexed and the original values of address are always output at these pins.
When the data bus width is 16 bits (BSZ1 and BSZ0 = B'10), A0 of SDRAM specifies a word
address. Therefore, connect this A0 pin of SDRAM to the A1 pin of the LSI; the A1 pin of
SDRAM to the A2 pin of the LSI, and so on. When the data bus width is 32 bits (BSZ1 and BSZ0
= B'11), the A0 pin of SDRAM specifies a longword address. Therefore, connect this A0 pin of
SDRAM to the A2 pin of the LSI; the A1 pin of SDRAM to the A3 pin of the LSI, and so on.
Rev. 2.00 Mar. 14, 2008 Page 312 of 1824
REJ09B0290-0200