SH7263 Datasheet, PDF (14/1862 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7260 Series

9.5.7 Burst ROM (Clocked Asynchronous) Interface.................................................... 352
9.5.8 SRAM Interface with Byte Selection ................................................................... 354
9.5.9 PCMCIA Interface................................................................................................ 359
9.5.10 Burst MPX-I/O Interface ...................................................................................... 366
9.5.11 Burst ROM (Clocked Synchronous) Interface...................................................... 371
9.5.12 Wait between Access Cycles ................................................................................ 372
9.5.13 Bus Arbitration ..................................................................................................... 379
9.5.14 Others.................................................................................................................... 381
Section 10 Direct Memory Access Controller (DMAC)................................... 385
10.1 Features.............................................................................................................................. 385
10.2 Input/Output Pins............................................................................................................... 388
10.3 Register Descriptions......................................................................................................... 389
10.3.1 DMA Source Address Registers (SAR)................................................................ 393
10.3.2 DMA Destination Address Registers (DAR)........................................................ 394
10.3.3 DMA Transfer Count Registers (DMATCR) ....................................................... 394
10.3.4 DMA Channel Control Registers (CHCR) ........................................................... 395
10.3.5 DMA Reload Source Address Registers (RSAR)................................................. 404
10.3.6 DMA Reload Destination Address Registers (RDAR)......................................... 405
10.3.7 DMA Reload Transfer Count Registers (RDMATCR) ........................................ 406
10.3.8 DMA Operation Register (DMAOR) ................................................................... 407
10.3.9 DMA Extension Resource Selectors 0 to 3 (DMARS0 to DMARS3).................. 411
10.4 Operation ........................................................................................................................... 414
10.4.1 Transfer Flow........................................................................................................ 414
10.4.2 DMA Transfer Requests ....................................................................................... 416
10.4.3 Channel Priority.................................................................................................... 422
10.4.4 DMA Transfer Types............................................................................................ 425
10.4.5 Number of Bus Cycles and DREQ Pin Sampling Timing .................................... 434
10.5 Usage Notes ....................................................................................................................... 438
10.5.1 Setting of the Half-End Flag and Generation of the Half-End Interrupt............... 438
10.5.2 Timing of DACK and TEND Outputs .................................................................. 438
10.5.3 Notice about using external request mode ............................................................ 439
10.5.4 Notice about using on-chip peripheral module request mode or
auto-request mode................................................................................................. 440
Section 11 Multi-Function Timer Pulse Unit 2 (MTU2)................................... 441
11.1 Features.............................................................................................................................. 441
11.2 Input/Output Pins............................................................................................................... 446
11.3 Register Descriptions......................................................................................................... 447
11.3.1 Timer Control Register (TCR).............................................................................. 451
Rev. 2.00 Mar. 14, 2008 Page xiv of xxxiv
REJ09B0290-0200