SH7263 Datasheet, PDF (1223/1862 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7260 Series

Section 24 AND/NAND Flash Memory Controller (FLCTL)
24.2 Input/Output Pins
The pin configuration of the FLCTL is listed in table 24.1.
Table 24.1 Pin Configuration
Pin
Name I/O
Corresponding Flash
Memory Pin
NAND Type AND Type
Function
FCE Output CE
CE
Chip Enable
Enables flash memory connected to this LSI.
NAF7 to I/O
NAF0
I/O7 to I/O0 I/O7 to I/O0 Data Input/Output
I/O pins for command, address, and data.
FCDE Output CLE
CDE
Command Latch Enable (CLE)
Asserted when a command is output.
Command Data Enable (CDE)
Asserted when a command is output.
FOE Output ALE
OE
Address Latch Enable (ALE)
Asserted when an address is output and negated when data is
input or output.
Output Enable (OE)
Asserted when data is input or when a status is read.
FSC
Output RE
SC
Read Enable (RE)
Reads data at the falling edge of RE.
Serial Clock (SC)
Inputs or outputs data synchronously with the SC.
FWE Output WE
WE
Write Enable
Flash memory latches a command, address, and data at the
rising edge of WE.
FRB
Input R/B
R/B
Ready/Busy
Indicates ready state at high level; indicates busy state at low
level.
—*
—
WP
RES
Write Protect/Reset
When this pin goes low, erroneous erasure or programming at
power on or off can be prevented.
—*
—
SE
—
Spare Area Enable
Used to access spare area. This pin must be fixed at low in
sector access mode.
Note: * Not supported in this LSI.
Rev. 2.00 Mar. 14, 2008 Page 1189 of 1824
REJ09B0290-0200