SH7263 Datasheet, PDF (1142/1862 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7260 Series

Section 21 CD-ROM Decoder (ROM-DEC)
21.3.18 Pre-ECC Correction Header: Seconds Data Register (HEAD01)
The pre-ECC correction header: seconds data register (HEAD01) indicates the seconds value in
the header before ECC correction.
Bit: 7
6
5
4
3
2
1
0
HEAD01[7:0]
Initial value: 0
0
0
0
0
0
0
0
R/W: R
R
R
R
R
R
R
R
Bit
7 to 0
Bit Name
HEAD01[7:0]
Initial
Value
All 0
R/W Description
R
Seconds Value in Header Before ECC Correction
21.3.19 Pre-ECC Correction Header: Frames (1/75 Second) Data Register (HEAD02)
The pre-ECC correction header: frames (1/75 second) data register (HEAD02) indicates the
frames value (1 frame = 1/75 second) in the header before ECC correction.
Bit: 7
6
5
4
3
2
1
0
HEAD02[7:0]
Initial value: 0
0
0
0
0
0
0
0
R/W: R
R
R
R
R
R
R
R
Bit
7 to 0
Bit Name
HEAD02[7:0]
Initial
Value
All 0
R/W Description
R
Frames Value in Header Before ECC Correction
Rev. 2.00 Mar. 14, 2008 Page 1108 of 1824
REJ09B0290-0200