SH7263 Datasheet, PDF (292/1862 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7260 Series

Section 9 Bus State Controller (BSC)
Bit
18 to 16
Bit Name
WW[2:0]
Initial
Value
000
15 to 13 ⎯
All 0
12, 11 SW[1:0] 00
R/W Description
R/W Number of Write Access Wait Cycles
Specify the number of cycles that are necessary for
write access.
000: The same cycles as WR[3:0] setting (number of
read access wait cycles)
001: No cycle
010: 1 cycle
011: 2 cycles
100: 3 cycles
101: 4 cycles
110: 5 cycles
111: 6 cycles
R
Reserved
These bits are always read as 0. The write value
should always be 0.
R/W Number of Delay Cycles from Address, CS5 Assertion
to RD, WE Assertion
Specify the number of delay cycles from address and
CS5 assertion to RD and WE assertion.
00: 0.5 cycles
01: 1.5 cycles
10: 2.5 cycles
11: 3.5 cycles
Rev. 2.00 Mar. 14, 2008 Page 258 of 1824
REJ09B0290-0200