SH7263 Datasheet, PDF (51/1862 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7260 Series

Section 1 Overview
Classification Symbol
I/O
Direct memory DREQ3 to
I
access controller DREQ0
(DMAC)
DACK3 to
O
DACK0
TEND1, TEND0 O
Multi-function TCLKA,
I
timer pulse unit TCLKB,
2 (MTU2)
TCLKC,
TCLKD
TIOC0A,
I/O
TIOC0B,
TIOC0C,
TIOC0D
TIOC1A,
I/O
TIOC1B
TIOC2A,
I/O
TIOC2B
TIOC3A,
I/O
TIOC3B,
TIOC3C,
TIOC3D
TIOC4A,
I/O
TIOC4B,
TIOC4C,
TIOC4D
Name
Function
DMA-transfer
request
Input pins to receive external
requests for DMA transfer.
DMA-transfer
request accept
Output pins for signals indicating
acceptance of external requests from
external devices.
DMA-transfer end Output pins for DMA transfer end.
output
MTU2 timer clock External clock input pins for the
input
timer.
MTU2 input
capture/output
compare
(channel 0)
MTU2 input
capture/output
compare
(channel 1)
MTU2 input
capture/output
compare
(channel 2)
MTU2 input
capture/output
compare
(channel 3)
MTU2 input
capture/output
compare
(channel 4)
The TGRA_0 to TGRD_0 input
capture input/output compare
output/PWM output pins.
The TGRA_1 and TGRB_1 input
capture input/output compare
output/PWM output pins.
The TGRA_2 and TGRB_2 input
capture input/output compare
output/PWM output pins.
The TGRA_3 to TGRD_3 input
capture input/output compare
output/PWM output pins.
The TGRA_4 and TGRB_4 input
capture input/output compare
output/PWM output pins.
Rev. 2.00 Mar. 14, 2008 Page 17 of 1824
REJ09B0290-0200