SH7263 Datasheet, PDF (1131/1862 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7260 Series

Section 21 CD-ROM Decoder (ROM-DEC)
21.3.7 HEAD20 to HEAD22 Representation Control Register (CROMCTL5)
The HEAD20 to HEAD22 representation control register (CROMCTL5) specifies the
representation mode for HEAD20 to HEAD22.
Bit: 7
-
Initial value: 0
R/W: R/W
6
-
0
R/W
5
-
0
R/W
4
-
0
R/W
3
-
0
R/W
2
-
0
R/W
1
0
-
MSF_
LBA_SEL
0
0
R/W R/W
Bit Bit Name
7 to 1 ⎯
Initial
Value
All 0
0
MSF_LBA_ 0
SEL
R/W Description
R/W Reserved
These bits are always read as 0. The write value should
always be 0.
R/W HEAD20 to HEAD22 Representation Mode
0: Header MSF is represented in BCD (decimal) as is
1: Total sector number is represented in HEX
(hexadecimal)
Rev. 2.00 Mar. 14, 2008 Page 1097 of 1824
REJ09B0290-0200