SH7263 Datasheet, PDF (1569/1862 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7260 Series

Section 30 I/O Ports
30.6.2 Port E Data Registers L (PEDRL)
PEDRL is a 16-bit readable/writable register that stores port E data. The PE15DR to PE0DR bits
correspond to the PE15/IOIS16/RTS3 to PE0/BS/RxD0/ADTRG pins, respectively.
When a pin function is general output, if a value is written to PEDRL, that value is output directly
from the pin, and if PEDRL is read, the register value is returned directly regardless of the pin
state.
When a pin function is general input, if PEDRL is read, the pin state, not the register value, is
returned directly. If a value is written to PEDRL, although that value is written into PEDRL, it
does not affect the pin state. Table 30.10 summarizes PEDRL read/write operation.
Bit: 15
PE15
DR
Initial value: 0
R/W: R/W
14
PE14
DR
0
R/W
13
PE13
DR
0
R/W
12
PE12
DR
0
R/W
11
PE11
DR
0
R/W
10
PE10
DR
0
R/W
9
PE9
DR
0
R/W
8
PE8
DR
0
R/W
7
PE7
DR
0
R/W
6
PE6
DR
0
R/W
5
PE5
DR
0
R/W
4
PE4
DR
0
R/W
3
PE3
DR
0
R/W
2
PE2
DR
0
R/W
1
PE1
DR
0
R/W
0
PE0
DR
0
R/W
Initial
Bit
Bit Name Value R/W Description
15
PE15DR 0
R/W See table 30.10.
14
PE14DR 0
R/W
13
PE13DR 0
R/W
12
PE12DR 0
R/W
11
PE11DR 0
R/W
10
PE10DR 0
R/W
9
PE9DR 0
R/W
8
PE8DR 0
R/W
7
PE7DR 0
R/W
6
PE6DR 0
R/W
5
PE5DR 0
R/W
4
PE4DR 0
R/W
3
PE3DR 0
R/W
2
PE2DR 0
R/W
1
PE1DR 0
R/W
0
PE0DR 0
R/W
Rev. 2.00 Mar. 14, 2008 Page 1535 of 1824
REJ09B0290-0200