SH7263 Datasheet, PDF (565/1862 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7260 Series

Section 11 Multi-Function Timer Pulse Unit 2 (MTU2)
(5) Cascaded Operation Example (d)
Figure 11.24 illustrates the operation when TCNT_1 and TCNT_2 have been cascaded and the
I2AE bit in TICCR has been set to 1 to include the TIOC2A pin in the TGRA_1 input capture
conditions. In this example, the IOA0 to IOA3 bits in TIOR_1 have selected TGRA_0 compare
match or input capture occurrence for the input capture timing while the IOA0 to IOA3 bits in
TIOR_2 have selected the TIOC2A rising edge for the input capture timing.
Under these conditions, as TIOR_1 has selected TGRA_0 compare match or input capture
occurrence for the input capture timing, the TIOC2A edge is not used for TGRA_1 input capture
condition although the I2AE bit in TICCR has been set to 1.
TCNT_0 value
TGRA_0
Compare match between TCNT_0 and TGRA_0
H'0000
TCNT_2 value
H'FFFF
H'D000
Time
H'0000
TCNT_1
TIOC1A
TIOC2A
TGRA_1
TGRA_2
H'0512
H'0513
Time
H'0513
H'D000
Figure 11.24 Cascaded Operation Example (d)
Rev. 2.00 Mar. 14, 2008 Page 531 of 1824
REJ09B0290-0200