SH7263 Datasheet, PDF (1592/1862 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7260 Series

Section 32 Power-Down Modes
Initial
Bit
Bit Name Value R/W Description
7
HIZ
0
R/W Port High Impedance
Selects whether the state of specific output pin is
retained or high impedance in software standby mode
or deep standby mode. As to which pins are
controlled, see appendix A, Pin States.
This bit must not be set while the TME bit in WTSCR
of the WDT is 1. To set the output pin to high-
impedance, set the HIZ bit to 1 only while the TME bit
is 0.
0: The pin state is retained in software standby mode
or deep standby mode.
1: The pin is set to high-impedance in software
standby mode or deep standby mode.
6
MSTP36 1
R/W Module Stop 36
When the MSTP36 bit is set to 1, the supply of the
clock to the IEB is halted.
0: IEB runs.
1: Clock supply to IEB is halted.
5
MSTP35 1
R/W Module Stop 35
When the MSTP35 bit is set to 1, the supply of the
clock to the MTU2 is halted.
0: MTU2 runs.
1: Clock supply to MTU2 is halted.
4
MSTP34 1
R/W Module Stop 34
When the MSTP34 bit is set to 1, the supply of the
clock to the SDHI0 is halted.
0: SDHI0 runs.
1: Clock supply to SDHI0 is halted.
3
MSTP33 1
R/W Module Stop 33
When the MSTP33 bit is set to 1, the supply of the
clock to the SDHI1 is halted.
0: SDHI1 runs.
1: Clock supply to SDHI1 is halted.
Rev. 2.00 Mar. 14, 2008 Page 1558 of 1824
REJ09B0290-0200