SH7263 Datasheet, PDF (429/1862 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7260 Series

Section 10 Direct Memory Access Controller (DMAC)
10.3.4 DMA Channel Control Registers (CHCR)
The DMA channel control registers (CHCR) are 32-bit readable/writable registers that control the
DMA transfer mode.
The DO, AM, AL, DL, and DS bits which specify the DREQ and DACK external pin functions
can be read and written to in channels 0 to 3, but they are reserved in channels 4 to 7. The TL bit
which specifies the TEND external pin function can be read and written to in channels 0 and 1, but
it is reserved in channels 2 to 7.
Bit: 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
TC
-
RLD RLD
SAR DAR
-
DAF SAF
-
DO TL
-
TE
MASK
HE
HIE
AM
AL
Initial value: 0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
R/W: R/W R R/W R/W R R/W R/W R R/W R/W R R/W R/(W)* R/W R/W R/W
Bit:
Initial value:
R/W:
15 14
DM[1:0]
0
0
R/W R/W
13 12
SM[1:0]
0
0
R/W R/W
11
0
R/W
10 9
RS[3:0]
0
0
R/W R/W
8
0
R/W
7
DL
0
R/W
6
DS
0
R/W
5
TB
0
R/W
4
3
TS[1:0]
0
0
R/W R/W
2
1
0
IE
TE DE
0
0
0
R/W R/(W)* R/W
Note: * Only 0 can be written to clear the flag after 1 is read.
Initial
Bit
Bit Name Value R/W Description
31
TC
0
R/W Transfer Count Mode
Specifies whether to transmit data once or for the
count specified in DMATCR by one transfer request.
This function is valid only in on-chip peripheral module
request mode. Note that when this bit is set to 0, the
TB bit must not be set to 1 (burst mode). When the
SCIF, IIC3, SSI, SRC, SDHI, FLCTL, or SSU is
selected for the transfer request source, this bit (TC)
must not be set to 1.
0: Transmits data once by one transfer request
1: Transmits data for the count specified in DMATCR
by one transfer request
30
⎯
0
R
Reserved
This bit is always read as 0. The write value should
always be 0.
Rev. 2.00 Mar. 14, 2008 Page 395 of 1824
REJ09B0290-0200