SH7263 Datasheet, PDF (1391/1862 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7260 Series

Section 25 USB 2.0 Host/Function Module (USB)
1. If IITV = 0
The buffer flush operation starts from the next frame after the pipe becomes valid.
2. In any cases other than IITV = 0
The buffer flush operation is carried out subsequent to the first normal transaction.
Figure 25.18 shows an example of the buffer flush function of this module. When an unanticipated
token is received prior to the interval frame, this module sends the written data or a zero-length
packet according to the buffer state.
Buffer A
Buffer B
Empty
Writing
Empty
Writing
ended
Writing
Transfer enabled
Writing ended
Empty Writing
Writing
ended
Transfer enabled
Figure 25.18 Example of Buffer Flush Function Operation
Figure 25.19 shows an example of this module generating an interval error. There are five types of
interval errors, as shown below. The interval error is generated at the timing indicated by (1) in the
figure, and the IN buffer flush function is activated.
If an interval error occurs during an IN transfers, the buffer flush function is activated; and if it
occurs during an OUT transfer, an NRDY interrupt is generated.
The OVRN bit should be used to distinguish between NRDY interrupts such as received packet
errors and overrun errors.
In response to tokens that are shaded in the figure, responses occur based on the buffer memory
status.
1. IN direction:
⎯ If the buffer is in the transmission enabled state, the data is transferred as a normal
response.
⎯ If the buffer is in the transmission disabled state, a zero-length packet is sent and an
underrun error occurs.
2. OUT direction:
⎯ If the buffer is in the reception enabled state, the data is received as a normal response.
⎯ If the buffer is in the reception disabled state, the data is discarded and an overrun error
occurs.
Rev. 2.00 Mar. 14, 2008 Page 1357 of 1824
REJ09B0290-0200