SH7263 Datasheet, PDF (472/1862 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7260 Series

Section 10 Direct Memory Access Controller (DMAC)
10.5 Usage Notes
10.5.1 Setting of the Half-End Flag and Generation of the Half-End Interrupt
When checking the status of the half-end flag of CHCR or using the reload function while the
half-end interrupt is enabled, note the following point.
The specification for the transfer count to be reloaded (the value in RDMATCR) should always be
the same as the transfer count that was initially specified (the value in DMATCR). If there is a
difference between the initial DMATCR setting and the RDMATCR setting, which is used for the
second and subsequent transfers, the half-end flag may be set before the transfer count reaches half
of the specified transfer count or not be set at all. This also applies to the half-end interrupt.
10.5.2 Timing of DACK and TEND Outputs
When the external memory is the MPX-I/O or burst MPX-I/O, the DACK output is asserted with
the timing of the data cycle. For details, see the respective figures in section 9.5.5, MPX-I/O
Interface, or section 9.5.10, Burst MPX-I/O Interface, in section 9, Bus State Controller (BSC).
When the memory is other than the MPX-I/O or burst MPX-I/O, the DACK output is asserted
with the same timing as the corresponding CS signal.
The TEND output does not depend on the type of memory and is always asserted with the same
timing as the corresponding CS signal.
Rev. 2.00 Mar. 14, 2008 Page 438 of 1824
REJ09B0290-0200