SH7263 Datasheet, PDF (132/1862 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7260 Series

Section 3 Floating-Point Unit (FPU)
The possibilities for exception handling caused by floating point operations are described in the
individual instruction descriptions. All exception events that originate in floating point operations
are assigned as the same FPU exception handling event. The meaning of an exception caused by a
floating point operation is determined by software by reading from FPSCR and interpreting the
information it contains. Also, the destination register is not changed when FPU exception handling
occurs.
Except for the above, the bit corresponding to source V, Z, O, U, or I is set to 1, and a default
value is generated as the operation result.
• Invalid operation (V): qNaN is generated as the result.
• Division by zero (Z): Infinity with the same sign as the unrounded value is generated.
• Overflow (O):
When rounding mode = RZ, the maximum normalized number, with the same sign as the
unrounded value, is generated.
When rounding mode = RN, infinity with the same sign as the unrounded value is generated.
• Underflow (U):
Zero with the same sign as the unrounded value is generated.
• Inexact exception (I): An inexact result is generated.
Rev. 2.00 Mar. 14, 2008 Page 98 of 1824
REJ09B0290-0200