SH7263 Datasheet, PDF (1611/1862 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7260 Series

Section 32 Power-Down Modes
32.2.14 Retention On-Chip RAM Trimming Register (DSRTR)
DSRTR is an 8-bit readable/writable register used to trim the standby current for the on-chip RAM
for data retention in deep standby mode. Only byte access is valid.
To retain data on the on-chip RAM for data retention in deep standby mode, be sure to write H'09
to this register before making a transition to deep standby mode.
This register is initialized after the assertion of the RES pin or exit from deep standby mode.
Note: When writing to this register, see section 32.4, Usage Notes.
Bit: 7
-
Initial value: 0
R/W: R
6
0
R/W
5
0
R/W
4
3
2
TRMD[6:0]
0
0
0
R/W R/W R/W
1
0
R/W
0
0
R/W
Bit
7
6 to 0
Initial
Bit Name Value R/W Description
⎯
0
R
Reserved
This bit is always read as 0. The write value should
always be 0.
TRMD[6:0] All 0
R/W Retention On-Chip RAM Trimming Data
These bits trim the standby current for the on-chip
RAM for data retention in deep standby mode.
Rev. 2.00 Mar. 14, 2008 Page 1577 of 1824
REJ09B0290-0200