SH7263 Datasheet, PDF (181/1862 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7260 Series

Section 6 Interrupt Controller (INTC)
6.3.2 Interrupt Control Register 0 (ICR0)
ICR0 is a 16-bit register that sets the input signal detection mode for the external interrupt input
pin NMI, and indicates the input level at the NMI pin.
Bit: 15 14 13 12 11 10 9
8
7
6
5
4
3
2
1
0
NMIL -
-
-
-
-
- NMIE -
-
-
-
-
-
-
-
Initial value: *
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
R/W: R
R
R
R
R
R
R R/W R
R
R
R
R
R
R
R
Note: * 1 when the NMI pin is high, and 0 when the NMI pin is low.
Bit
Bit Name
15
NMIL
14 to 9 ⎯
8
NMIE
7 to 0 ⎯
Initial
Value
*
All 0
0
All 0
R/W Description
R NMI Input Level
Sets the level of the signal input at the NMI pin. The
NMI pin level can be obtained by reading this bit. This
bit cannot be modified.
0: Low level is input to NMI pin
1: High level is input to NMI pin
R Reserved
These bits are always read as 0. The write value should
always be 0.
R/W NMI Edge Select
Selects whether the falling or rising edge of the
interrupt request signal on the NMI pin is detected.
0: Interrupt request is detected on falling edge of NMI
input
1: Interrupt request is detected on rising edge of NMI
input
R Reserved
These bits are always read as 0. The write value should
always be 0.
Rev. 2.00 Mar. 14, 2008 Page 147 of 1824
REJ09B0290-0200