SH7263 Datasheet, PDF (1840/1862 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7260 Series

Main Revisions for this Edition
Item
Page
32.2.12 Deep Standby 1573,
Cancel Source Select 1574
Register (DSSSR)
32.3.2 Software
Standby Mode
1580
(2) Canceling Software
Standby Mode
(3) Note on Release
from Software Standby
Mode
1581
Revision (See Manual for Details)
Description of bits 8 to 0 amended
Cancellation of Deep Standby Mode by …
0: Deep standby mode is not canceled by …
1: Deep standby mode is canceled by …
Description amended
• Canceling by an interrupt
… When software standby mode is canceled by the falling
edge of the NMI pin, the NMI pin should be high when the
CPU enters software standby mode (when the clock pulse
stops) and should be low when software standby mode is
canceled (when the clock is initiated after oscillation
settling). When software standby mode is canceled by the
rising edge of the NMI pin, the NMI pin should be low when
the CPU enters software standby mode (when the clock
pulse stops) and should be high when software standby
mode is canceled (when the clock is initiated after
oscillation settling). (The same applies to the IRQ pin.)
Description amended
… If, however, a SLEEP instruction and an interrupt other than
NMI and IRQ are generated at the same time, cancellation of
software standby mode may occur due to acceptance of the
interrupt.
Rev. 2.00 Mar. 14, 2008 Page 1806 of 1824
REJ09B0290-0200