SH7263 Datasheet, PDF (13/1862 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7260 Series

Section 8 Cache .................................................................................................211
8.1 Features.............................................................................................................................. 211
8.1.1 Cache Structure..................................................................................................... 211
8.2 Register Descriptions ......................................................................................................... 214
8.2.1 Cache Control Register 1 (CCR1) ........................................................................ 214
8.2.2 Cache Control Register 2 (CCR2) ........................................................................ 216
8.3 Operation ........................................................................................................................... 220
8.3.1 Searching Cache ................................................................................................... 220
8.3.2 Read Access.......................................................................................................... 222
8.3.3 Prefetch Operation (Only for Operand Cache) ..................................................... 222
8.3.4 Write Operation (Only for Operand Cache).......................................................... 223
8.3.5 Write-Back Buffer (Only for Operand Cache)...................................................... 223
8.3.6 Coherency of Cache and External Memory .......................................................... 225
8.4 Memory-Mapped Cache .................................................................................................... 226
8.4.1 Address Array ....................................................................................................... 226
8.4.2 Data Array ............................................................................................................ 227
8.4.3 Usage Examples.................................................................................................... 229
8.4.4 Notes ..................................................................................................................... 229
Section 9 Bus State Controller (BSC)................................................................231
9.1 Features.............................................................................................................................. 231
9.2 Input/Output Pins ............................................................................................................... 234
9.3 Area Overview ................................................................................................................... 236
9.3.1 Address Map ......................................................................................................... 236
9.3.2 Data Bus Width and Pin Function Setting in Each Area....................................... 237
9.4 Register Descriptions ......................................................................................................... 238
9.4.1 Common Control Register (CMNCR) .................................................................. 239
9.4.2 CSn Space Bus Control Register (CSnBCR) (n = 0 to 7) ..................................... 242
9.4.3 CSn Space Wait Control Register (CSnWCR) (n = 0 to 7) .................................. 247
9.4.4 SDRAM Control Register (SDCR)....................................................................... 281
9.4.5 Refresh Timer Control/Status Register (RTCSR)................................................. 285
9.4.6 Refresh Timer Counter (RTCNT)......................................................................... 287
9.4.7 Refresh Time Constant Register (RTCOR) .......................................................... 288
9.5 Operation ........................................................................................................................... 289
9.5.1 Endian/Access Size and Data Alignment.............................................................. 289
9.5.2 Normal Space Interface......................................................................................... 296
9.5.3 Access Wait Control ............................................................................................. 301
9.5.4 CSn Assert Period Expansion ............................................................................... 303
9.5.5 MPX-I/O Interface................................................................................................ 304
9.5.6 SDRAM Interface ................................................................................................. 308
Rev. 2.00 Mar. 14, 2008 Page xiii of xxxiv
REJ09B0290-0200