SH7263 Datasheet, PDF (1351/1862 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7260 Series

Section 25 USB 2.0 Host/Function Module (USB)
Suspended state detection
(when SUSP = 1, DVST is set to 1.)
Powered
state
(DVSQ = 100)
Suspended
state
(DVSQ = 100)
USB bus reset detection
(when URST = 1, DVST is set to 1.)
Resume (RESM is set to 1)
USB bus reset detection
(when URST = 1, DVST is set to 1.)
Suspended state detection
(when SUSP = 1, DVST is set to 1.)
Default
state
(DVSQ = 001)
Suspended
state
(DVSQ = 101)
Resume (RESM is set to 1)
SetAddress execution
(Address = 0)
(when URST = 1, DVST is set to 1.)
SetAddress execution
(when SADR = 1, DVST is set to 1.)
Suspended state detection
(when SUSP = 1, DVST is set to 1.)
Address
Suspended
state
state
(DVSQ = 010)
(DVSQ = 110)
Resume (RESM is set to 1)
SetConfiguration
execution
(configuration value = 0)
(when SADR = 1,
DVST is set to 1.)
SetConfiguration execution
(configuration value = 0)
(when SCFG = 1, DVST is set to 1.)
Suspended state detection
(when SUSP = 1, DVST is set to 1.)
Configured
Suspended
state
(DVSQ = 011)
state
(DVSQ = 111)
Resume (RESM is set to 1)
Note: The URST, SADR, SCFG and SUSP bits in parentheses are enable bits that permit or block setting of the DVST bit to 1 by this module
when the corresponding stage transition is detected. (These enable bits are on INTENB0.)
Stage transitions are carried out even if setting the DVST bit to 1 is inhibited by these bits.
Figure 25.6 Device State Transitions
Rev. 2.00 Mar. 14, 2008 Page 1317 of 1824
REJ09B0290-0200