SH7263 Datasheet, PDF (1468/1862 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7260 Series

Section 27 Sampling Rate Converter (SRC)
Figure 27.1 shows a block diagram of the SRC.
Peripheral bus
SRCID
SRCOD
Input data FIFO
(32 bits × 16 stages)
Input buffer memory
(16 bits × 64 words × 2)
ch0
Intermediate buffer
memory
(16 bits × 64 words × 2)
ch0
Output data FIFO
(32 bits × 8 stages)
ch1
ch1
SRCIDCTRL
SRCODCTRL
SRCCTRL
SRCSTAT
Input/output controller
Coefficient ROM
Registers
Interrupt/DMA transfer requests
[Legend]
SRCID:
SRC input data register
SRCOD: SRC output data register
SRCIDCTRL: SRC input data control register
SRCODCTRL: SRC output data control register
SRCCTRL: SRC control register
SRCSTAT: SRC status register
Figure 27.1 Block Diagram of SRC
Rev. 2.00 Mar. 14, 2008 Page 1434 of 1824
REJ09B0290-0200