SH7263 Datasheet, PDF (1149/1862 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7260 Series

Section 21 CD-ROM Decoder (ROM-DEC)
21.3.32 Post-ECC Correction Header: Mode Data Register (HEAD23)
The post-ECC correction header: mode data register (HEAD23) indicates the mode value in the
header after ECC correction.
Bit: 7
6
5
4
3
2
1
0
HEAD23[7:0]
Initial value: 0
0
0
0
0
0
0
0
R/W: R
R
R
R
R
R
R
R
Bit Bit Name
7 to 0 HEAD23[7:0]
Initial
Value R/W Description
All 0 R
Mode Value in Header After ECC Correction
21.3.33 Post-ECC Correction Subheader: File Number (Byte 16) Data Register
(SHEAD20)
The post-ECC correction subheader: file number (byte 16) data register (SHEAD20) indicates the
file number value in the subheader after ECC correction (byte 16).
Bit: 7
6
5
4
3
2
1
0
SHEAD20[7:0]
Initial value: 0
0
0
0
0
0
0
0
R/W: R
R
R
R
R
R
R
R
Bit Bit Name
Initial
Value R/W Description
7 to 0 SHEAD20[7:0] All 0 R
Indicate file number value in the subheader after ECC
correction (byte 16).
Rev. 2.00 Mar. 14, 2008 Page 1115 of 1824
REJ09B0290-0200