SH7263 Datasheet, PDF (1159/1862 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7260 Series

Section 21 CD-ROM Decoder (ROM-DEC)
21.3.47 CD-ROM Decoder Reset Status Register (RSTSTAT)
The CD-ROM decoder reset status register (RSTSTAT) indicates that the RAM in the CD-ROM
decoder has been cleared.
Bit: 7
6
5
4
3
2
1
0
RAM
CLRST
-
-
-
-
-
-
-
Initial value: 0
0
0
0
0
0
0
0
R/W: R
R
R
R
R
R
R
R
Initial
Bit Bit Name Value
7
RAMCLRST 0
6 to 0 ⎯
All 0
R/W Description
R
This bit is set to 1 on completion of RAM clearing after
the RAMRST bit in ROMDECRST is set to 1. The bit is
cleared by writing a 0 to the RAMRST bit.
R
Reserved
These bits are always read as 0 and cannot be modified.
21.3.48 SSI Data Control Register (SSI)
The SSI data control register (SSI) provides various settings related to the data stream. For the
operation corresponding to the setting of this register, refer to section 21.4.1, Endian Conversion
for Data in the Input Stream.
Bit: 7
6
5
4
BYTEND BITEND BUFEND0[1:0]
Initial value: 0
0
0
1
R/W: R/W R/W R/W R/W
3
2
BUFEND1[1:0]
1
0
R/W R/W
1
-
0
R/W
0
-
0
R/W
Initial
Bit Bit Name Value R/W Description
7
BYTEND
0
R/W Specifies the endian of input data from the SSI module.
When this bit is set to 1, the bytes in STRMDIN0 and
STRMDIN1 are swapped, as are those in STRMDIN2
and STRMDIN3.
6
BITEND
0
R/W Specifies treatment of the bit order of the input data
from the SSI module.
When this bit is set to 1, the bits within each byte are
rearranged to place them in reverse order, bit 0 → bit 7
to bit 7 → bit 0.
Rev. 2.00 Mar. 14, 2008 Page 1125 of 1824
REJ09B0290-0200