SH7263 Datasheet, PDF (1733/1862 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7260 Series

Section 35 Electrical Characteristics
35.4.3 Bus Timing
Table 35.8 Bus Timing
Conditions: VCC = PLLVCC = USBDVCC = 1.1 to 1.3 V, PVCC = USBDPVCC = 3.0 to 3.6 V,
AVCC = 3.0 to 3.6 V, USBAVCC = 1.1 to 1.3 V, USBAPVCC = 3.0 to 3.6 V,
VSS = PLLVSS = PVSS = AVSS = USBDVSS = USBAVSS = USBDPVSS =
USBAPVSS = 0 V, Ta = −40 to 85 °C
Item
Address delay time 1
Address delay time 2
Address delay time 3
Address setup time
Chip enable setup time
Address hold time
BS delay time
CS delay time 1
CS delay time 2
Read write delay time 1
Read write delay time 2
Read strobe delay time
Read data setup time 1
Read data setup time 2
Symbol
t
AD1
Bφ = 66.66 MHz*¹*²
Min.
Max.
1
13
Unit
ns
t_AD2
1/2t_cyc
1/2t_cyc + 13 ns
t
1/2t
1/2t + 13 ns
AD3
cyc
cyc
t_AS
0
—
ns
t
0
—
ns
CS
t_AH
0
—
ns
t_BSD
—
13
ns
t
1
13
ns
CSD1
t_CSD2
t
RWD1
1/2t_cyc
1
1/2t_cyc + 13 ns
13
ns
t
RWD2
t_RSD
1/2t
cyc
1/2t_cyc
1/2t + 13 ns
cyc
1/2t_cyc + 13 ns
t
1/2t + 13 —
ns
RDS1
cyc
t
8
—
ns
RDS2
Figure
Figures 35.13 to
35.38, 35.40 to
35.44
Figure 35.21
Figures 35.39, 35.40
Figures 35.13 to
35.16, 35.21
Figures 35.13 to
35.16, 35.21
Figures 35.13 to
35.16
Figures 35.13 to
35.35, 35.39, 35.41
to 35.44
Figures 35.13 to
35.38, 35.41 to
35.44
Figures 35.39, 35.40
Figures 35.13 to
35.38, 35.41 to
35.44
Figures 35.39, 35.40
Figures 35.13 to
35.17, 35.19 to
35.21, 35.41, 35.42
Figures 35.13 to
35.17, 35.19, 35.20,
35.41 to 35.44
Figures 35.18, 35.22
to 35.25, 35.30 to
35.32
Rev. 2.00 Mar. 14, 2008 Page 1699 of 1824
REJ09B0290-0200