SH7263 Datasheet, PDF (839/1862 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7260 Series

Section 16 Synchronous Serial Communication Unit (SSU)
16.4.5 SSU Mode
In SSU mode, data communications are performed via four lines: clock line (SSCK), data input
line (SSI or SSO), data output line (SSI or SSO), and chip select line (SCS).
In addition, the SSU supports bidirectional mode in which a single pin functions as data input and
data output lines.
(1) Initial Settings in SSU Mode
Figure 16.4 shows an example of the initial settings in SSU mode. Before data transfer, clear both
the TE and RE bits in SSER to 0 to set the initial values.
Note:
Before changing operating modes and communications formats, clear both the TE and RE
bits to 0. Although clearing the TE bit to 0 sets the TDRE bit to 1, clearing the RE bit to 0
does not change the values of the RDRF and ORER bits and SSRDR. Those bits retain the
previous values.
Start setting initial values
Clear the TE and RE bits in SSER to 0
[1] Set PFC for external pins to be used
(SSCK, SSI, SSO, and SCS)
[2]
Specify the MSS, BIDE, SOL,
CSS1, and CSS0 bits in SSCRH
[3] ^{Clear the SSUMS bit in SSCRL to 0 and}
specify bits DATS1 and DATS0
[1] Make appropriate settings in the PFC for the external pins to be used.
[2] Specify master/slave mode selection, bidirectional mode enable,
SSO pin output value selection, SSCK pin selection, and SCS pin
selection.
[3] Selects SSU mode and specify transmit/receive data length.
[4] Specify MSB first/LSB first selection, clock polarity selection,
clock phase selection, and transfer clock rate selection.
[5] Enables/disables interrupt request to the CPU.
[4]
Specify the MLS, CPOS, CPHS, CKS2,
CKS1, and CKS0 bits in SSMR
[5]
Specify TEIE, TIE, RIE, TE, RE
and CEIE bits in SSER all together
End
Figure 16.4 Example of Initial Settings in SSU Mode
Rev. 2.00 Mar. 14, 2008 Page 805 of 1824
REJ09B0290-0200