SH7263 Datasheet, PDF (1652/1862 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7260 Series

Section 34 List of Registers
Module
Name Register Name
Abbreviation
ROM-
DEC
ROMDEC enable control register CROMEN
Sync code-based synchronization CROMSY0
control register
Decoding mode control register CROMCTL0
EDC/ECC check control register CROMCTL1
Automatic decoding stop control CROMCTL3
register
Decoding option setting control
register
CROMCTL4
HEAD20 to HEAD22
representation control register
CROMCTL5
Sync code status register
CROMST0
Post-ECC header error status
register
CROMST1
Post-ECC subheader error status CROMST3
register
Header/subheader validity check CROMST4
status register
Mode determination and link sector CROMST5
detection status register
ECC/EDC error status register
CROMST6
Buffer status register
CBUFST0
Decoding stoppage source status CBUFST1
register
Buffer overflow status register
CBUFST2
Pre-ECC correction header:
minutes data register
HEAD00
Pre-ECC correction header:
seconds data register
HEAD01
Pre-ECC correction header:
HEAD02
frames (1/75 second) data register
Pre-ECC correction header:
mode data register
HEAD03
Number
of Bits Address
8
H'FFFC2000
8
H'FFFC2001
Access
Size
8
8
8
H'FFFC2002 8
8
H'FFFC2003 8
8
H'FFFC2005 8
8
H'FFFC2006 8
8
H'FFFC2007 8
8
H'FFFC2008 8
8
H'FFFC2009 8
8
H'FFFC200B 8
8
H'FFFC200C 8
8
H'FFFC200D 8
8
H'FFFC200E 8
8
H'FFFC2014 8
8
H'FFFC2015 8
8
H'FFFC2016 8
8
H'FFFC2018 8
8
H'FFFC2019 8
8
H'FFFC201A 8
8
H'FFFC201B 8
Rev. 2.00 Mar. 14, 2008 Page 1618 of 1824
REJ09B0290-0200