SH7263 Datasheet, PDF (1609/1862 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7260 Series

Section 32 Power-Down Modes
32.2.13 Deep Standby Cancel Source Flag Register (DSFR)
DSFR is a 16-bit readable/writable register composed of two types of bits. One is the flag that
confirms which interrupt canceled deep standby mode. The other is the bit that releases the state of
pins after canceling deep standby mode. When deep standby mode is canceled by an interrupt
(NMI or IRQ) or a manual reset, this register retains the previous data although power-on reset
exception handling is executed. When deep standby mode is canceled by a power-on reset, this
register is initialized to H’0000. Only word access is valid.
All flags must be cleared immediately before transition to deep standby mode.
Note: When writing to this register, see section 32.4, Usage Notes.
Bit: 15 14 13 12 11 10 9
8
7
6
5
4
3
2
1
0
IO
KEEP
-
-
-
-
- MRESF NMIF IRQ7F IRQ6F IRQ5F IRQ4F IRQ3F IRQ2F IRQ1F IRQ0F
Initial value: 0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
R/W: R/(W)* R
R
R
R
R R/(W)* R/(W)* R/(W)* R/(W)* R/(W)* R/(W)* R/(W)* R/(W)* R/(W)* R/(W)*
Note: * Only 0 can be written after reading 1 to clear the flag.
Bit
Bit Name
15
IOKEEP
14 to 10 ⎯
9
MRESF
Initial
Value
0
All 0
0
R/W Description
R/(W)* Release of Pin State Retention
Releases the retention of the pin state after canceling
deep standby mode
0: Pin state not retained
[Clearing condition]
Writing 0 after reading 1
1: Pin state retained
[Setting condition]
When deep standby mode is entered
R
Reserved
These bits are always read as 0. The write value
should always be 0.
R/(W)* MRES Flag
0: No interrupt on MRES pin
1: Interrupt on MRES pin
Rev. 2.00 Mar. 14, 2008 Page 1575 of 1824
REJ09B0290-0200