SH7263 Datasheet, PDF (343/1862 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7260 Series

Section 9 Bus State Controller (BSC)
As shown in figure 9.16, two sets of SDRAMs of 32 Mbytes or smaller can be connected to the
same CS space by using RASU, RASL, CASU, and CASL. In this case, a total of 8 banks are
assigned to the same CS space: 4 banks specified by RASL and CASL, and 4 banks specified by
RASU and CASU. When accessing the address with A25 = 0, RASL and CASL are asserted.
When accessing the address with A25 = 1, RASU and CASU are asserted.
This LSI
A15
A2
CKE
CKIO
CSn
RASU
CASU
RASL
CASL
RD/WR
D31
D16
DQMUU
DQMUL
D15
D0
DQMLU
DQMLL
Unused
Unused
64M SDRAM
(1M × 16-bit × 4-bank)
A13
A0
CKE
CLK
CS
RAS
CAS
WE
I/O15
I/O0
DQMU
DQML
A13
A0
CKE
CLK
CS
RAS
CAS
WE
I/O15
I/O0
DQMU
DQML
Figure 9.14 Example of 32-Bit Data Width SDRAM Connection
(RASU and CASU are Not Used)
Rev. 2.00 Mar. 14, 2008 Page 309 of 1824
REJ09B0290-0200