SH7263 Datasheet, PDF (1601/1862 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7260 Series

Section 32 Power-Down Modes
32.2.8 System Control Register 2 (SYSCR2)
SYSCR2 is an 8-bit readable/writable register that enables or disables write to the on-chip RAM
(high-speed). Only byte access is valid.
When an RAMWE bit is set to 1, the corresponding on-chip RAM (high-speed) area is enabled.
When an RAMWE bit is cleared to 0, the corresponding on-chip RAM (high-speed) area cannot
be written to. In this case, writing to the on-chip RAM (high-speed) is ignored. The initial value of
an RAMWE bit is 1.
Note that when clearing the RAME bit to 0 to disable the on-chip RAM (high-speed), be sure to
execute an instruction to read from or write to the same arbitrary address in each page before
setting the RAMWE bit. If such an instruction is not executed, the data last written to each page
may not be written to the on-chip RAM (high-speed). Furthermore, an instruction to access the on-
chip RAM (high-speed) should not be located immediately after the instruction to write to
SYSCR2. If an on-chip RAM (high-speed) access instruction is set, normal access is not
guaranteed.
When setting the RAME bit to 1 to enable write to the on-chip RAM (high-speed), an instruction
to read SYSCR2 should be located immediately after the instruction to write to SYSCR2. If an
instruction to access the on-chip RAM (high-speed) is located immediately after the instruction to
write to SYSCR2, normal access is not guaranteed.
Note: When writing to this register, see section 32.4, Usage Notes.
Bit: 7
6
5
4
3
2
1
0
-
-
-
-
RAM RAM RAM RAM
WE3 WE2 WE1 WE0
Initial value: 1
1
1
1
1
1
1
1
R/W: R R R R R/W R/W R/W R/W
Bit
7 to 4
3
Initial
Bit Name Value R/W Description
⎯
All 1
R
Reserved
These bits are always read as 1. The write value
should always be 1.
RAMWE3 1
R/W RAM Write Enable 3 (corresponding area of on-chip
RAM (high-speed): page 3*)
0: Write to on-chip RAM (high-speed) disabled
1: Write to on-chip RAM (high-speed) enabled
Rev. 2.00 Mar. 14, 2008 Page 1567 of 1824
REJ09B0290-0200