SH7263 Datasheet, PDF (1838/1862 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7260 Series

Main Revisions for this Edition
Item
31.1 Features
32.1.1 Power-Down
Modes
Table 32.1 States of
Power-Down Modes
Page
1548
1552,
1553
Revision (See Manual for Details)
Description amended
• Ports
…
The on-chip RAM for data retention has one read/write port
and is connected to the peripheral bus.
Table and notes amended
State*¹
Power-
Down
Mode
On-Chip
RAM
(High-
Speed)
Cash
Memory
On-Chip
RAM
(for Data
Retention)
Softw
standby
mode
Halted
(contents
are
held*⁵*⁶)
Halted
(contents
are held*⁵)
Notes: 3. Setting the bits RAMKP3 to RAMKP0 in the
RAMKP register to 1 enables to retain the data in
the corresponding area on the on-chip RAM during
the transition to deep standby. However, the stored
contents are initialized when deep standby mode is
canceled by a power-on reset.
…
5. The stored contents are initialized when software
standby mode is canceled by a power-on reset.
6. The stored contents can be retained even when
software standby mode is canceled by a power-on
reset by disabling access to the on-chip RAM (high-
speed) by means of the RAME bits in the SYSCR1
register or the RAMWE bits in the SYSCR2
register.
Rev. 2.00 Mar. 14, 2008 Page 1804 of 1824
REJ09B0290-0200