SH7263 Datasheet, PDF (1837/1862 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7260 Series

Main Revisions for this Edition
Item
25.4.2 Interrupt
Functions
(10) DTCH Interrupt
Page
1321
25.4.4 Buffer Memory 1340
(2) FIFO Port Functions
(h) Method of Changing
Setting of MBW Bits
when Selected
CURPIPE Is Set to
Buffer Memory Read
Direction
25.4.5 Control
Transfers (DCP)
1347
(2) Control Transfers
when the Function
Controller Function is
Selected
(c) Status Stage
27.5.1 Note on Register 1452
Access
27.5.2 Note on Flush
Processing
29.3 Switching Pin
Function of Port A
1517
Table 29.9 Switching
Pin Function of
PA6/AN6/DA0 and
PA7/AN7/DA1
30.1 Features
1519
Revision (See Manual for Details)
Description amended
The DTCH interrupt is generated if disconnection of the device
is detected during full-speed operation when the host controller
function has been selected. Note that the DTCH interrupt
cannot be used in high-speed mode. Clear DTCHE to 0 in
high-speed mode. To detect disconnection during high-speed
operation, additional processing is necessary, such as
performing periodic control transfers of standard requests and
determining disconnection if no response is returned from the
peripheral side.
Newly added
Description amended
1. For control read transfers:
The zero-length packet is received from the USB host, and
this module sends an ACK response.
2. For control write transfers and no-data control transfers:
This module sends a zero-length packet and receives an
ACK response from the USB host.
Title added
Newly added
Table title amended and table replaced
Description amended
• Port C: PC0 to PC14
… If the pull-up or pull-down resistors become necessary to fix
the pin level, use the resistor of 10 kΩ or smaller.
Rev. 2.00 Mar. 14, 2008 Page 1803 of 1824
REJ09B0290-0200