SH7263 Datasheet, PDF (978/1862 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7260 Series

Section 19 Controller Area Network (RCAN-TL1)
⎯ Time reference message with Next_is_Gap set has been received when working in time-
trigger mode. Please note that when a Next_is_Gap is received the application is
responsible to stop all transmission at the end of the current basic cycle (including test
modes)
⎯ Message error has occurred when in test mode. Note: If a Message Overload condition
occurs when in Test Mode, then this bit will not be set.
Bit 13: IRR13
0
1
Description
Timer (TCNTR) has not overrun in event-trigger mode (including test modes)
(Initial value)
Time reference message with Next_is_Gap has not been received in time-
trigger mode (including test modes)
Message error has not occurred in test mode
[Clearing condition] Writing 1
[Setting condition]
Timer (TCNTR) has overrun and changed from H'FFFF to H'0000 in event-
trigger mode (including test modes)
Time reference message with Next_is_Gap has been received in time-trigger
mode (including test modes)
Message error has occurred in test mode
Bit 12 – Bus activity while in sleep mode (IRR12): IRR12 indicates that a CAN bus activity is
present. While the RCAN-TL1 is in sleep mode and a dominant bit is detected on the CAN bus,
this bit is set. This interrupt is cleared by writing a '1' to this bit position. Writing a '0' has no
effect. If auto wakeup is not used and this interrupt is not requested it needs to be disabled by the
related interrupt mask register. If auto wake up is not used and this interrupt is requested it should
be cleared only after recovering from sleep mode. This is to avoid that a new falling edge of the
reception line causes the interrupt to get set again.
Please note that the setting time of this interrupt is different from the clearing time of GSR4.
Bit 12: IRR12
0
1
Description
Bus idle state (Initial value)
[Clearing condition] Writing 1
CAN bus activity detected in RCAN-TL1 sleep mode
[Setting condition]
Dominant bit level detection on the Rx line while in sleep mode
Rev. 2.00 Mar. 14, 2008 Page 944 of 1824
REJ09B0290-0200