SH7263 Datasheet, PDF (1406/1862 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7260 Series

Section 26 LCD Controller (LCDC)
Initial
Bit
Bit Name Value R/W Description
10
MCNT
0
R/W M Signal Control
Sets whether or not to output the LCD's current-
alternating signal of the LCD module.
0: M (AC line modulation) signal is output
1: M signal is not output
9
CL1CNT 0
R/W CL1 (Horizontal Sync Signal) Control
Sets whether or not to enable CL1 output during the
vertical retrace period.
0: CL1 is output during vertical retrace period
1: CL1 is not output during vertical retrace period
8
CL2CNT 1
R/W CL2 (Dot Clock of LCD Module) Control
Sets whether or not to enable CL2 output during the
vertical and horizontal retrace period.
0: CL2 is output during vertical and horizontal retrace
period
1: CL2 is not output during vertical and horizontal
retrace period
7, 6
⎯
All 0 R
Reserved
These bits are always read as 0. The write value
should always be 0.
Rev. 2.00 Mar. 14, 2008 Page 1372 of 1824
REJ09B0290-0200