SH7263 Datasheet, PDF (1597/1862 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7260 Series

Section 32 Power-Down Modes
32.2.6 Standby Control Register 6 (STBCR6)
STBCR6 is an 8-bit readable/writable register that controls the operation of each module in
power-down modes. Only byte access is valid.
Note: When writing to this register, see section 32.4, Usage Notes.
Bit: 7
6
5
4
3
2
1
0
MSTP MSTP MSTP MSTP MSTP MSTP
67 66
65
64
63
62
-
MSTP
60
Initial value: 1
1
1
1
1
1
1
1
R/W: R/W R/W R/W R/W R/W R/W R R/W
Initial
Bit
Bit Name Value R/W Description
7
MSTP67 1
R/W Module Stop 67
When the MSTP67 bit is set to 1, the supply of the
clock to the SSI0 is halted.
0: SSI0 runs.
1: Clock supply to SSI0 is halted.
6
MSTP66 1
R/W Module Stop 66
When the MSTP66 bit is set to 1, the supply of the
clock to the SSI1 is halted.
0: SSI1 runs.
1: Clock supply to SSI1 is halted.
5
MSTP65 1
R/W Module Stop 65
When the MSTP65 bit is set to 1, the supply of the
clock to the SSI2 is halted.
0: SSI2 runs.
1: Clock supply to SSI2 is halted.
4
MSTP64 1
R/W Module Stop 64
When the MSTP64 bit is set to 1, the supply of the
clock to the SSI3 is halted.
0: SSI3 runs.
1: Clock supply to SSI3 is halted.
Rev. 2.00 Mar. 14, 2008 Page 1563 of 1824
REJ09B0290-0200