SH7263 Datasheet, PDF (1341/1862 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7260 Series

Section 25 USB 2.0 Host/Function Module (USB)
Figure 25.2 shows a diagram relating to interrupts of this module.
Interrupt
request
Generation
circuit
INTENB0
VBSE
RSME
SOFE
DVSE
CTRE
BEMPE
NRDYE
BRDYE
INTSTS0
VBINT
RESM
SOFR
DVST
CTRT
BEMP
NRDY
BRDY
BCHGE
DTCHE
SIGNE
SACKE
INTENB1
BCHG
DTCH
SIGN
SACK
INTSTS1
INTENB0
URST
SADR
SCFG
SUSP
WDST
RDST
CMPL
SERR
USB bus reset detected
Set_Address detected
Set_Configuration
detected
Suspended state detected
Control write data stage
Control read data stage
Completion of control
transfer
Control transfer error
Control transfer setup
reception
BEMP interrupt enable register
b7 ^... b1 b0
b7
:
:
...
b1
b0
NRDY interrupt enable register
b7 ... b1 b0
b7
:
:
...
b1
b0
BRDY interrupt enable register
b7 ^... b1 b0
b7
:
:
...
b1
b0
Figure 25.2 Items Relating to Interrupts
Rev. 2.00 Mar. 14, 2008 Page 1307 of 1824
REJ09B0290-0200