SH7263 Datasheet, PDF (297/1862 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7260 Series

Section 9 Bus State Controller (BSC)
Bit
17, 16
Bit Name
BW[1:0]
15 to 11 ⎯
10 to 7 W[3:0]
Initial
Value
00
All 0
1010
R/W Description
R/W Number of Burst Wait Cycles
Specify the number of wait cycles to be inserted
between the second or subsequent access cycles in
burst access.
00: No cycle
01: 1 cycle
10: 2 cycles
11: 3 cycles
R
Reserved
These bits are always read as 0. The write value
should always be 0.
R/W Number of Access Wait Cycles
Specify the number of wait cycles to be inserted in the
first access cycle.
0000: No cycle
0001: 1 cycle
0010: 2 cycles
0011: 3 cycles
0100: 4 cycles
0101: 5 cycles
0110: 6 cycles
0111: 8 cycles
1000: 10 cycles
1001: 12 cycles
1010: 14 cycles
1011: 18 cycles
1100: 24 cycles
1101: Reserved (setting prohibited)
1110: Reserved (setting prohibited)
1111: Reserved (setting prohibited)
Rev. 2.00 Mar. 14, 2008 Page 263 of 1824
REJ09B0290-0200