SH7263 Datasheet, PDF (596/1862 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7260 Series

Section 11 Multi-Function Timer Pulse Unit 2 (MTU2)
Timer output control register settings
OLSN bit: 0 (initial output: high; active level: low)
OLSP bit: 0 (initial output: high; active level: low)
TCNT_3, 4 value
TCNT_3
TCNT_4
Positive phase
output
Negative phase
output
TDDR
TGRA_4
Initial output
Active level
Time
Complementary
PWM mode
(TMDR setting)
TCNT_3, 4 count start
(TSTR setting)
Figure 11.45 Example of Initial Output in Complementary PWM Mode (2)
Rev. 2.00 Mar. 14, 2008 Page 562 of 1824
REJ09B0290-0200