SH7263 Datasheet, PDF (1119/1862 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7260 Series

Section 21 CD-ROM Decoder (ROM-DEC)
21.3 Register Descriptions
The ROM-DEC has the following registers.
Table 21.1 Register Configuration
Name
Initial
Abbreviation R/W Value Address
Access
Size
ROMDEC enable control register
CROMEN R/W H'00 H'FFFC2000 8
Sync code-based synchronization control CROMSY0
register
R/W H'89 H'FFFC2001 8
Decoding mode control register
CROMCTL0 R/W H'82 H'FFFC2002 8
EDC/ECC check control register
CROMCTL1 R/W H'D1 H'FFFC2003 8
Automatic decoding stop control register CROMCTL3 R/W H'00 H'FFFC2005 8
Decoding option setting control register CROMCTL4 R/W H'00 H'FFFC2006 8
HEAD20 to HEAD22 representation
control register
CROMCTL5 R/W H'00 H'FFFC2007 8
Sync code status register
CROMST0 R H'00 H'FFFC2008 8
Post-ECC header error status register
CROMST1 R H'00 H'FFFC2009 8
Post-ECC subheader error status register CROMST3 R H'00 H'FFFC200B 8
Header/subheader validity check status CROMST4 R
register
H'00 H'FFFC200C 8
Mode determination and link sector
detection status register
CROMST5 R H'00 H'FFFC200D 8
ECC/EDC error status register
CROMST6 R H'00 H'FFFC200E 8
Buffer status register
CBUFST0 R H'00 H'FFFC2014 8
Decoding stoppage source status register CBUFST1 R H'00 H'FFFC2015 8
Buffer overflow status register
CBUFST2 R H'00 H'FFFC2016 8
Pre-ECC correction header:
minutes data register
HEAD00
R H'00 H'FFFC2018 8
Pre-ECC correction header:
seconds data register
HEAD01
R H'00 H'FFFC2019 8
Pre-ECC correction header:
frames (1/75 second) data register
HEAD02
R H'00 H'FFFC201A 8
Pre-ECC correction header:
mode data register
HEAD03
R H'00 H'FFFC201B 8
Rev. 2.00 Mar. 14, 2008 Page 1085 of 1824
REJ09B0290-0200