SH7263 Datasheet, PDF (468/1862 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7260 Series

Section 10 Direct Memory Access Controller (DMAC)
10.4.5 Number of Bus Cycles and DREQ Pin Sampling Timing
(1) Number of Bus Cycles
When the DMAC is the bus master, the number of bus cycles is controlled by the bus state
controller (BSC) in the same way as when the CPU is the bus master. For details, see section 9,
Bus State Controller (BSC).
(2) DREQ Pin Sampling Timing
Figures 10.13 to 10.16 show the DREQ input sampling timings in each bus mode.
CKIO
Bus cycle
DREQ
(Rising)
DACK
(Active-high)
CPU
CPU
1st acceptance
Non sensitive period
DMAC
CPU
2nd acceptance
Acceptance start
Figure 10.13 Example of DREQ Input Detection in Cycle Steal Mode Edge Detection
CKIO
Bus cycle
DREQ
(Overrun 0 at
high level)
DACK
(Active-high)
CPU
CPU
1st acceptance
Non sensitive period
DMAC
CPU
2nd acceptance
Acceptance
start
CKIO
Bus cycle
DREQ
(Overrun 1 at
high level)
DACK
(Active-high)
CPU
CPU
1st acceptance
Non sensitive period
DMAC
CPU
2nd acceptance
Acceptance
start
Figure 10.14 Example of DREQ Input Detection in Cycle Steal Mode Level Detection
Rev. 2.00 Mar. 14, 2008 Page 434 of 1824
REJ09B0290-0200