SH7263 Datasheet, PDF (1836/1862 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7260 Series

Main Revisions for this Edition
Item
25.3.12 Interrupt
Enabled Register 1
(INTENB1)
Page
1260
25.3.17 Interrupt Status 1270
Register 1 (INTSTS1)
25.3.30 DCP Control 1289
Register (DCPCTR)
25.4.1 System Control 1302
Revision (See Manual for Details)
Table amended
Initial
Bit
Bit Name
Value R/W Description
12
DTCHE
0
R/W Disconnection Detection Interrupt Enable during Full-
Speed Operation
The disconnection detection using this bit is valid
only when the host controller function is selected and
full-speed operation is performed. During high-speed
operation, software should be used to detect
disconnection by detecting no response from a
function or by another appropriate method.
0: Interrupt output disabled
1: Interrupt output enabled
Note:
When high-speed operation established
(RHST = 11) is determined after a reset
handshake, keep DTCHE cleared to 0 during
high-speed communication.
Table amended
Initial
Bit
Bit Name
Value R/W Description
12
DTCH
0
R/W* Disconnection Detection Interrupt Status During Full-
Speed Operation
The disconnection detection using this bit is valid
only when the host controller function is selected and
full-speed operation is performed. During high-speed
operation, the disconnection detection, such as
detection of no response from a function, should be
executed using software.
0: DTCH interrupts not generated
1: DTCH interrupts generated
Note:
When high-speed operation established
(RHST = 11) is determined after a reset
handshake, keep DTCHE cleared to during
high-speed operation. Also, the DTCH bit
may be set to 1 during high-speed
communication. Therefore, do not fail to clear
DTCH to 0 after high-speed communication
completes.
Note 4. amended
4. To change the SQSET or SQCLR bit in this register and
that in PIPEnCTR in succession (to change the PID
sequence toggle bits of multiple pipes in succession), an
access cycle of at least 120 ns and 5 or more bus clock
cycles is required.
Title amended
(2) Controller Function
Selection
Description deleted
This module can select the host controller function or function
controller function using the DCFM bit in SYSCFG.
Rev. 2.00 Mar. 14, 2008 Page 1802 of 1824
REJ09B0290-0200