SH7263 Datasheet, PDF (905/1862 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7260 Series

Section 18 Serial Sound Interface (SSI)
18.3 Register Description
The SSI has the following registers. Note that explanation in the text does not refer to the
channels.
Table 18.2 Register Description
Channel Register Name
Abbrevia-
tion
R/W Initial Value Address
Access
Size
0
Control register 0
SSICR_0
R/W H’00000000 H'FFFEC000 32
Status register 0
SSISR_0
R/W* H’02000003 H'FFFEC004 32
Transmit data register 0 SSITDR_0 R/W H’00000000 H'FFFEC008 32
Receive data register 0 SSIRDR_0 R
H’00000000 H'FFFEC00C 32
1
Control register 1
SSICR_1
R/W H’00000000 H'FFFEC800 32
Status register 1
SSISR_1
R/W* H’02000003 H'FFFEC804 32
Transmit data register 1 SSITDR_1 R/W H’00000000 H'FFFEC808 32
Receive data register 1 SSIRDR_1 R
H’00000000 H'FFFEC80C 32
2
Control register 2
SSICR_2
R/W H’00000000 H'FFFED000 32
Status register 2
SSISR_2
R/W* H’02000003 H'FFFED004 32
Transmit data register 2 SSITDR_2 R/W H’00000000 H'FFFED008 32
Receive data register 2 SSIRDR_2 R
H’00000000 H'FFFED00C 32
3
Control register 3
SSICR_3
R/W H’00000000 H'FFFED800 32
Status register 3
SSISR_3
R/W* H’02000003 H'FFFED804 32
Transmit data register 3 SSITDR_3 R/W H’00000000 H'FFFED808 32
Receive data register 3 SSIRDR_3 R
H’00000000 H'FFFED80C 32
Note: * Although bits 26 and 27 in this register can be read from or written to, bits other than
these are read-only. For details, refer to section 18.3.2, Status Register (SSISR).
Rev. 2.00 Mar. 14, 2008 Page 871 of 1824
REJ09B0290-0200