SH7263 Datasheet, PDF (1819/1862 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7260 Series

Main Revisions for this Edition
Item
Page
9.5.1 Endian/Access 289
Size and Data Alignment
9.5.3 Access Wait
301
Control
9.5.6 SDRAM Interface 346
(12) Power-On
Sequence
9.5.7 Burst ROM
353
(Clocked Asynchronous)
Interface
Figure 9.35 Burst ROM
Access Timing (Clocked
Asynchronous) (Bus
Width = 32 Bits, 16-Byte
Transfer (Number of
Burst 4), Wait Cycles
Inserted in First Access
= 2, Wait Cycles Inserted
in Second and
Subsequent Access
Cycles = 1)
9.5.13 Bus Arbitration 381
Figure 9.55 Bus
Arbitration Timing (Clock
Mode 2)
Revision (See Manual for Details)
Description amended
… For example, with big endian and a 32-bit bus width, WE3
corresponds to the 0th address, which is represented by WE0
when little endian has been selected. Area 0 cannot be set to
little endian mode. In addition, fetching instructions from a little
endian area can be difficult because 32-bit and 16-bit accesses
are mixed, so big endian mode should be used for instruction
execution.
Description amended
…It is possible for areas 1, 4, 5, and 7 to insert wait cycles
independently in read access and in write access. …
Description amended
In order to use SDRAM, mode setting must first be made for
SDRAM after waiting for the designated pause interval after
powering on. This pause interval should be provided by a
power-on reset generating circuit or software.
Figure amended
T1 Tw Tw T2B Twb T2B Twb T2B Twb T2
CKIO
Figure title amended
Rev. 2.00 Mar. 14, 2008 Page 1785 of 1824
REJ09B0290-0200