SH7263 Datasheet, PDF (1282/1862 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7260 Series

Section 25 USB 2.0 Host/Function Module (USB)
25.3.6 FIFO Port Registers (CFIFO, D0FIFO, D1FIFO)
CFIFO, D0FIFO and D1FIFO are port registers that are used to read data from the FIFO buffer
memory and writing data to the FIFO buffer memory.
There are three FIFO ports: the CFIFO, D0FIFO and D1FIFO ports. Each FIFO port is configured
of a port register that handles reading of data from the buffer memory and writing of data to the
buffer memory, a select register that is used to select the pipe assigned to the FIFO port, a control
register, and registers used specially for port functions (an SIE register used exclusively for the
CFIFO port and a transaction counter register used exclusively for the DnFIFO port).
These registers are initialized by a power-on reset or a software reset.
Bit: 31
Initial value: 0
R/W: R/W
30
0
R/W
29
0
R/W
28
0
R/W
27
0
R/W
26
0
R/W
25 24 23 22
FIFOPORT[31:16]
0
0
0
0
R/W R/W R/W R/W
21
0
R/W
20
0
R/W
19
0
R/W
18
0
R/W
17
0
R/W
16
0
R/W
Bit: 15
Initial value: 0
R/W: R/W
14
0
R/W
13
0
R/W
12
0
R/W
11
0
R/W
10
0
R/W
9
8
7
6
FIFOPORT[15:0]
0
0
0
0
R/W R/W R/W R/W
5
0
R/W
4
0
R/W
3
0
R/W
2
0
R/W
1
0
R/W
0
0
R/W
Initial
Bit
Bit Name
Value R/W Description
31 to 0 FIFOPORT All 0
[31:0]
R/W FIFO Port
These bits are used to read receive data from the
buffer memory and write transmit data to the buffer
memory.
Notes: 1. The DCP can access the buffer memory only through the CFIFO port. Accessing the
buffer memory using DMA transfer can be performed only through the D0FIFO and
D1FIFO ports.
2. Accessing the DnFIFO port using the CPU must be performed in conjunction with the
functions and restrictions of the DnFIFO port (using the transaction counter, etc.).
3. When using functions specific to the FIFO port, the selected pipe cannot be changed
(using the transaction counter, etc.).
4. Registers configuring a FIFO port do not affect other FIFO ports.
5. The same pipe should not be assigned to two or more FIFO ports.
6. There are two sorts of buffer memory states: the access right is on the CPU side and it
is on the SIE side. When the buffer memory access right is on the SIE side, the memory
cannot be properly accessed from the CPU.
7. The pipe configuration of the pipe selected for the FIFO port should not be changed.
Rev. 2.00 Mar. 14, 2008 Page 1248 of 1824
REJ09B0290-0200