SH7263 Datasheet, PDF (1589/1862 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7260 Series

Section 32 Power-Down Modes
32.2.1 Standby Control Register (STBCR)
STBCR is an 8-bit readable/writable register that specifies the state of the power-down mode.
Only byte access is valid.
Note: When writing to this register, see section 32.4, Usage Notes.
Bit: 7
6
5
4
3
2
1
0
STBY DEEP -
-
-
-
-
-
Initial value: 0
0
0
0
0
0
0
0
R/W: R/W R/W R
R
R
R
R
R
Initial
Bit
Bit Name Value R/W
7
STBY
0
R/W
6
DEEP
0
R/W
5 to 0 ⎯
All 0
R
[Legend]
x:
Don't care
Description
Software Standby, Deep Standby
Specifies transition to software standby mode or
deep standby mode.
0x: Executing SLEEP instruction puts chip into
sleep mode.
10: Executing SLEEP instruction puts chip into
software standby mode.
11: Executing SLEEP instruction puts chip into deep
standby mode.
Reserved
These bits are always read as 0. The write value
should always be 0.
Rev. 2.00 Mar. 14, 2008 Page 1555 of 1824
REJ09B0290-0200