SH7263 Datasheet, PDF (29/1862 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7260 Series

Section 26 LCD Controller (LCDC)................................................................1365
26.1 Features............................................................................................................................ 1365
26.2 Input/Output Pins ............................................................................................................. 1367
26.3 Register Configuration..................................................................................................... 1368
26.3.1 LCDC Input Clock Register (LDICKR) ............................................................. 1369
26.3.2 LCDC Module Type Register (LDMTR) ........................................................... 1371
26.3.3 LCDC Data Format Register (LDDFR).............................................................. 1374
26.3.4 LCDC Scan Mode Register (LDSMR) ............................................................... 1376
26.3.5 LCDC Start Address Register for Upper Display Data Fetch (LDSARU) ......... 1378
26.3.6 LCDC Start Address Register for Lower Display Data Fetch (LDSARL) ......... 1379
26.3.7 LCDC Line Address Offset Register for Display Data Fetch (LDLAOR) ......... 1380
26.3.8 LCDC Palette Control Register (LDPALCR)..................................................... 1381
26.3.9 Palette Data Registers 00 to FF (LDPR00 to LDPRFF) ..................................... 1382
26.3.10 LCDC Horizontal Character Number Register (LDHCNR) ............................... 1383
26.3.11 LCDC Horizontal Sync Signal Register (LDHSYNR) ....................................... 1384
26.3.12 LCDC Vertical Display Line Number Register (LDVDLNR) ........................... 1385
26.3.13 LCDC Vertical Total Line Number Register (LDVTLNR)................................ 1386
26.3.14 LCDC Vertical Sync Signal Register (LDVSYNR) ........................................... 1387
26.3.15 LCDC AC Modulation Signal Toggle Line Number Register (LDACLNR) ..... 1388
26.3.16 LCDC Interrupt Control Register (LDINTR) ..................................................... 1389
26.3.17 LCDC Power Management Mode Register (LDPMMR) ................................... 1392
26.3.18 LCDC Power-Supply Sequence Period Register (LDPSPR) .............................. 1394
26.3.19 LCDC Control Register (LDCNTR)................................................................... 1396
26.3.20 LCDC User Specified Interrupt Control Register (LDUINTR).......................... 1397
26.3.21 LCDC User Specified Interrupt Line Number Register (LDUINTLNR) ........... 1399
26.3.22 LCDC Memory Access Interval Number Register (LDLIRNR) ........................ 1400
26.4 Operation ......................................................................................................................... 1401
26.4.1 LCD Module Sizes which can be Displayed in this LCDC ................................ 1401
26.4.2 Limits on the Resolution of Rotated Displays, Burst Length,
and Connected Memory (SDRAM) .................................................................... 1402
26.4.3 Color Palette Specification ................................................................................. 1409
26.4.4 Data Format ........................................................................................................ 1410
26.4.5 Setting the Display Resolution............................................................................ 1413
26.4.6 Power Management Registers............................................................................. 1413
26.4.7 Operation for Hardware Rotation ....................................................................... 1418
26.5 Clock and LCD Data Signal Examples............................................................................ 1421
26.6 Usage Notes ..................................................................................................................... 1431
26.6.1 Procedure for Halting Access to Display Data Storage VRAM
(Synchronous DRAM in Area 3) ........................................................................ 1431
Rev. 2.00 Mar. 14, 2008 Page xxix of xxxiv
REJ09B0290-0200